Flip chip packaging technology has found wide-spread use because of its advantage in size, performance, flexibility, reliability and cost over other packaging methods. Flip chip packaging employs direct electrical connection of face-down integrated circuit (IC) chips onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip bond pads, replacing older wire bonding technology where face-up chips sit on substrates with wire connection to each bond pad. Many of the flip chip bumping techniques developed in recent years have focused on realizing bumps or solderable metallizations directly on the peripheral bond pads of a semiconductor chip. Solder bumping by screen printing solder paste can be used for chip I/O pitches down to 200 micron. However, with increasing IC complexity, the IC pin count has also increased drastically, so that if only peripheral pads were used, pitches that are less than 60 micron would be necessary. Therefore, in order to package these IC chips using flip-chip technology, the peripheral I/O pads are usually redistributed into area array pads with larger pads and a relaxed pitch. Such redistribution is typically accomplished by physically connecting the peripheral pads to the area array pads using conducting leads formed on the semiconductor chip.
Redistribution of I/O pads for flip chip packaging typically involves several process steps such as: (1) Ni/Au bumping of peripheral bond pads; (2) spinning of dielectric layer; (3) photo imaging for opening of Ni/Au bond pads; (4) formation of seed layer; (5) full area copper deposition; (6) photo masking for defining the redistribution lines; (7) copper etching; (8) spinning of solder masks and photo imaging for opening of redistributed pads; (9) Ni/Au bumping of redistributed pads; and (10) solder stencil printing. A cross-sectional view of a redistributed bump pad is shown in FIG. 1.
During flip chip packaging, the IC chip with bump array is placed face-down on a substrate with a matching bump array, and the assembly is heated to make a solder connection. The solder bumps in the matching bump array on the substrate are routed to a ball grid array (BGA) attached to the substrate via connection lines in the substrate. With the increasing density of the bump array, customized substrates with multilayered routing are typically used for today's flip chip ICs in order to fan-out all traces of the connection lines. FIG. 2 illustrates a portion of a flip-chip package of an IC chip with redistributed bump arrays. The bump array are placed on matching bump pads on a top side of the substrate. The matching bump pads are then connected to substrate BGA pads for attaching the BGA on a bottom side of the substrate via six layers of routing lines and vias that couple between these layers. The six layers of routing lines include two layers of signal trace lines L1 and L2, one VSS plane, one VCC plane, one VCCN plane, and one BGA land layer. The substrate unit cost increases drastically due to the additional layer count and advanced design rules to lay out the substrate routing lines. Therefore, there is a need to reduce substrate unit cost by using standard or semi-standard substrates with fewer routing layers and less stringent design rules.